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? semiconductor components industries, llc, 2007 july, 2007 - rev. 5 1 publication order number: NB4N316M/d NB4N316M 3.3 v anylevel receiver to cml driver/translator with input hysteresis 2.0 ghz clock / 2.5 gb/s data the NB4N316M is a differential clock or data receiver and will accept anylevel input signals: lvpecl, cml, lvcmos, lvttl, or lvds. these signals will be translated to cml, operating up to 2.0 ghz or 2.5 gb/s, respectively. as such, the NB4N316M is ideal for sonet, gige, fiber channel, backplane and other clock or data distribution applications. the cml outputs are 16 ma open collector (see figure 18) which requires resistor (r l ) load path to v tt termination voltage (see figure 19). the open collector cml outputs must be terminated to v tt at power up. the differential outputs produce currentCmode logic (cml) compatible levels when the receiver is loaded with 50 or 25 loads connected to 1.8 v, 2.5 v or 3.3 v supplies. this simplifies device interface by eliminating a need for coupling capacitors. the NB4N316M features an input threshold hysteresis of approximately 25 mv, providing increased noise immunity and stability. the device is offered in a small 8-pin tssop package (msop-8 compatible). application notes, models, and support documentation are available at www.onsemi.com . features ? maximum input clock frequency > 2.0 ghz ? maximum input data rate > 2.5 gb/s ? typically 1 ps of rms clock jitter ? typically 10 ps of data dependent jitter ? 550 ps typical propagation delay ? 150 ps typical rise and fall times ? differential cml outputs ? 25 mv of receiver input threshold hysteresis ? operating range: v cc = 3.0 v to 3.6 v with v ee = 0 v and v tt = 1.8 v to 3.6 v ? functionally compatible with existing 2.5 v / 3.3 v lvel, lvep, ep, and sg devices ? -40 c to +85 c ambient operating temperature ? these are pb-free devices* *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagram* http://onsemi.com tssop-8 dt suffix case 948r 1 8 e316 alyw 1 8 see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information a = assembly location l = wafer lot y = year w = work week = pb-free package *for additional marking information, refer to application note and8002/d. figure 1. functional block diagram q q d d (note: microdot may be in either location)
NB4N316M http://onsemi.com 2 figure 2. pinout (top view) and logic diagram 1 2 3 45 6 7 8 q v ee v cc d q d v bb nc table 1. pin description pin name i/o description 1 nc - no connect. 2 d ecl, cml, lvcmos, lvds, lvttl input noninverted differential input. (note 1) 3 d ecl, cml, lvcmos, lvds, lvttl input inverted differential input. (note 1) 4 v bb - internally generated reference voltage supply. 5 v ee - negative supply voltage. 6 q cml output inverted differential output. typically terminated with 50 resistor to v tt . 7 q cml output noninverted differential output. typically terminated with 50 resistor to v tt . 8 v cc - positive supply voltage. 1. in the differential configuration if no signal is applied on d/d input, then the device will be susceptible to self-oscillation.
NB4N316M http://onsemi.com 3 table 2. attributes characteristics value esd protection human body model machine model > 1000 v > 70 v moisture sensitivity (note 1) 8-tssop level 3 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 225 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = -0.5 v 4 v v ee negative power supply v cc = +0.5 v -4 v v i positive input negative input v ee = 0 v v cc = 0 v v i = v cc +0.4 v v i = v ee C0.4 v 4 -4 v v v o output voltage minimum maximum v ee + 600 v cc + 400 mv mv t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) (note 2) 0 lfpm 500 lfpm tssop-8 tssop-8 190 130 c/w c/w jc thermal resistance (junction-to-case) 1s2p (note 2) tssop-8 41 to 44 c/w t sol wave solder < 3 sec @ 260 c 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. jedec standard multilayer board - 1s2p (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB4N316M http://onsemi.com 4 table 4. dc characteristics, clock inputs, cml outputs v cc = 3.0 v to 3.6 v, v ee = 0 v, t a = -40 c to +85 c symbol characteristic min typ max unit i cc power supply current (inputs and outputs open) 20 30 ma r l = 50 , v tt = 3.6 v to 2.5 v v oh output high voltage (note 3) v tt - 60 v tt - 10 v tt mv v ol output low voltage (note 3) v tt - 1100 v tt - 800 v tt - 640 mv |v od | differential output voltage magnitude 640 780 1000 mv r l = 25 , v tt = 3.6 v to 2.5 v 5% v oh output high voltage (note 3) v tt - 60 v tt - 10 v tt mv v ol output low voltage (note 3) v tt - 550 v tt - 400 v tt - 320 mv |v od | differential output voltage magnitude 320 390 500 mv r l = 50 , v tt = 1.8 v 5% v oh output high voltage (note 3) v tt - 170 v tt - 10 v tt mv v ol output low voltage (note 3) v tt - 1100 v tt - 800 v tt - 640 mv |v od | differential output voltage magnitude 570 780 1000 mv r l = 25 , v tt = 1.8 v 5% v oh output high voltage (note 3) v tt - 85 v tt - 10 v tt mv v ol output low voltage (note 3) v tt - 500 v tt - 400 v tt - 320 mv |v od | differential output voltage magnitude 285 390 500 mv differential input driven single-ended (figures 14 and 16) v th input threshold reference voltage range (note 5) v ee v cc mv v ih single-ended input high voltage v th + 100 v cc + 400 mv v il single-ended input low voltage v ee - 400 v th - 100 mv v bb internally generated reference voltage supply (loaded with -100 a) v cc - 1500 v cc - 1400 v cc - 1300 mv differential inputs driven differentially (figures 15 and 17) v ihd differential input high voltage v ee v cc + 400 mv v ild differential input low voltage v ee - 400 v cc - 100 mv v cmr input common mode range (differential configuration) v ee v cc mv v id(hyst) differential input voltage hysteresis (v ihd - v ild ) 25 mv |v id | differential input voltage magnitude (|v ihd - v ild |) (note 7) 100 v cc - v ee mv c in input capacitance (note 7) 1.5 pf note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. cml outputs require r l receiver termination resistors to v tt for proper operation. outputs must be connected through r l to v tt at power up. the output parameters vary 1:1 with v tt . v tt = 1.71 v to 3.6 v. 4. input parameters vary 1:1 with v cc . 5. v th is applied to the complementary input when operating in single-ended mode. 6. v cmr (min) varies 1:1 with v ee , v cmr max varies 1:1 with v cc . 7. parameter guaranteed by design and evaluation but not tested in production.
NB4N316M http://onsemi.com 5 table 5. ac characteristics v cc = 3.0 v to 3.6 v, v ee = 0 v; (note 8) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude (r l = 50 ) f in 1 ghz (see figure 12) f in 1.5 ghz f in 2.0 ghz 550 400 200 660 640 400 550 400 200 660 640 400 550 400 200 660 640 400 mv v outpp output voltage amplitude (r l = 25 ) f in 1 ghz (see figure 12) f in 1.5 ghz f in 2.0 ghz 280 280 200 370 360 300 280 280 200 370 360 400 280 280 200 370 360 400 mv f data maximum operating data rate 1.5 2.5 1.5 2.5 1.5 2.5 gb/s t plh , t phl propagation delay to output differential @ 0.25 ghz 350 550 750 350 550 750 350 550 750 ps t skew duty cycle skew (note 9) device to device skew (note 13) 2 20 20 100 2 20 20 100 2 20 20 100 ps t jitter rms random clock jitter r l = 50 and r l = 25 (note 11) f in = 750 mhz f in = 1.5 ghz f in = 2.0 ghz peak-to-peak data dependent jitter r l = 50 f data = 1.5 gb/s (note 12) f data = 2.5 gb/s peak-to-peak data dependent jitter r l = 25 f data = 1.5 gb/s (note 12) f data = 2.5 gb/s 1 1 1 15 20 5 10 3 3 3 55 85 35 35 1 1 1 15 20 5 10 3 3 3 55 85 35 35 1 1 1 15 20 5 10 3 3 3 55 85 35 35 ps v inpp input voltage swing/sensitivity (differential configuration) (note 10) 200 200 200 mv t r t f output rise/fall times @ 0.25 ghz q, q (20% - 80%) 150 300 150 300 150 300 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. measured by forcing v inpp (min) from a 50% duty cycle clock source. all output loaded with an external r l = 50 and r l = 25 to v tt . outputs must be connected through r l to v tt at power up. input edge rates 150 ps (20% - 80%). 9. duty cycle skew is measured between differential outputs using the deviations of the sum of t pw- and t pw+ @ 0.25 ghz. 10. v inpp (max) cannot exceed v cc - v ee . input voltage swing is a single-ended measurement operating in differential mode. 11. additive rms jitter with 50% duty cycle clock signal. 12. additive peak-to-peak data dependent jitter with input nrz data signal (prbs 2 23 -1). 13. device to device skew is measured between outputs under identical transition @ 0.5 ghz. figure 3. output voltage amplitude (v outpp ) versus input clock frequency (f in ) at ambient temperature (typical) 0 100 200 300 400 500 600 700 800 0.75 1 1.25 1.5 1.75 2 r l = 50 r l = 25 input clock frequency (ghz) output voltage amplitude (mv) (v cc - v ee = 3.3 v v tt = 3.3 v @ 25 c v in = 100 mv) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.75 1 1.25 1.5 1.75 2 input clock frequency (ghz) output voltage amplitude (mv) (v cc - v ee = 3.0 v v tt = 1.71 v @25 c v in = 100 mv) r l = 50 r l = 25 0.5 0.5
NB4N316M http://onsemi.com 6 NB4N316M 0 10 20 30 40 50 60 70 80 0.5 0.75 1 1.25 1.5 1.75 2 -40 c 25 c 85 c input clock frequency (ghz) time (ps) figure 4. data dependent jitter vs. frequency and temperature (v cc - v ee = 3.3 v; v tt = 3.3 v @ 25 c; v in = 100 mv; prbs 2 23 -1; r l = 50 0 5 10 15 20 25 30 35 0.5 0.75 1 1.25 1.5 1.75 2 25 c -40 c 85 c input clock frequency (ghz) time (ps) figure 5. data dependent jitter vs. frequency and temperature (v cc - v ee = 3.3 v; v tt = 3.3 v @ 25 c; v in = 100 mv; prbs 2 23 -1; r l = 25 300 350 400 450 500 550 600 -40 25 85 figure 6. typical propagation delay vs. temperature (v cc - v ee = 3.3 v; v tt = 3.3 v @ 25 c; v in = 100 mv; r l = 50 ) temperature ( c) time (ps) t pd figure 7. typical propagation delay vs. input offset voltage (v cc - v ee = 3.3 v; v tt = 3.3 v @ 25 c; v in = 100 mv r l = 50 ) 300 350 400 450 500 550 600 t pd input offset voltage (v) time (ps) v ee - 0.5 v v cc + 0.5 v v cc v ee 2 0.25 0.25 figure 8. supply current vs. temperature 0 5 10 15 20 25 30 35 -40 25 85 i cc temperature ( c) current (ma)
NB4N316M http://onsemi.com 7 figure 9. typical differential output waveform at 750 mb/s (r l = 50 left plot, r l = 25 right plot, v in = 100 mv, system ddj = 24 ps) figure 10. typical differential output waveform 1.5 gb/s (r l = 50 left plot, r l = 25 right plot, v in = 100 mv, system ddj = 25 ps) ddj = 5 ps time (266.8 ps/div) voltage (200 mv/div) time (133.2 ps/div) voltage (200 mv/div) time (266.8 ps/div) voltage (100 mv/div) time (133.2 ps/div) voltage (100 mv/div) ddj = 3 ps ddj = 5 ps ddj = 12 ps figure 11. typical differential output waveform 2.5 gb/s (r l = 50 left plot, r l = 25 right plot, v in = 100 mv, system ddj = 24 ps) time (80 ps/div) voltage (200 mv/div) time (80 ps/div) voltage (100 mv/div) ddj = 20 ps ddj = 7 ps
NB4N316M http://onsemi.com 8 figure 12. ac reference measurement d d q q t phl t plh v inpp = v ih (d) - v il (d) v outpp = v oh (q) - v ol (q) figure 13. typical termination for output driver and device evaluation (see application note and8020/d - termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc - 2.0 v figure 14. differential input driven single-ended figure 15. differential inputs driven differentially figure 16. v th diagram figure 17. v cmr diagram d v cc gnd v ih v ihmin v ihmax v thmax v th v th v thmin v cmmax v cmmax d v cmr v cc gnd d d v th v th d d v ilmax v il v ilmin d v ilclkmax v ihclkmax v id = v ihd - v ild v ildtyp v ihdtyp v ildmin v ihdmin
NB4N316M http://onsemi.com 9 d d v cc r c r c figure 18. cml input and output structure v ee 1.25 k 1.25 k 1.25 k 1.25 k input esd input esd input esd input esd internal current source v ee 16 ma current source in q q in input output
NB4N316M http://onsemi.com 10 figure 19. typical examples of the application interface receiver a receiver b v ccb = 1.8 v 2.5 v or 3.3 v v cca = 1.8 v 2.5 v or 3.3 v 50 50 50 50 50 50 v ttb = v ccb v ttb = v ccb v tta = v cca z = 50 z = 50 z = 50 z = 50 NB4N316M receiver c receiver d v ccd = 1.8 v 2.5 v or 3.3 v v ccc = 1.8 v 2.5 v or 3.3 v v ccc = 3.3 v v ee = 0 v 100 100 75 75 v ttd = v ccd v ttc = v ccc z = 75 z = 75 z = 100 z = 100 NB4N316M NB4N316M NB4N316M v ee = 0 v v ccd = 3.3 v v ee = 0 v v ccb = 3.3 v v cca = 3.3 v v ee = 0 v
NB4N316M http://onsemi.com 11 ordering information device package shipping ? NB4N316Mdtg tssop-8 (pb-free) 100 units / rail NB4N316Mdtr2g tssop-8 (pb-free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d - ecl clock distribution techniques an1406/d - designing with pecl (ecl at +5.0 v) an1503/d - eclinps i/o spice modeling kit an1504/d - metastability and the eclinps family an1568/d - interfacing between lvds and ecl an1672/d - the ecl translator guide and8001/d - odd number counters design and8002/d - marking and date codes and8020/d - termination of ecl logic devices and8066/d - interfacing with eclinps and8090/d - ac characteristics of ecl devices
NB4N316M http://onsemi.com 12 package dimensions dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 -u- s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) -t- -v- -w- 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop-8 dt suffix plastic tssop package case 948r-02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guar antee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by custom er's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 NB4N316M/d anylevel and eclinps are trademarks of semiconductor components industries, llc (scillc). literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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